1. Field of the Invention
The present invention relates to a display device and a display system using the same, and more particularly, to a display device which enables a high-definition and multi-gradation image display with low power consumption and a display system using the same.
2. Description of the Related Art
In recent years, a technique has been progressing rapidly in which a polycrystalline silicon thin film is formed on a substrate having an insulating surface, such as a glass substrate or a plastic substrate. The research and development has been actively made on a display device in which a TFT (thin film transistor), which is formed by using the polycrystalline silicon thin film as its active layer, is provided as a switching element in a pixel portion and an active matrix display device in which a circuit for driving pixels is formed in the periphery of a pixel portion.
The largest advantages of the above display device are generally thinness, lightness in weight, and low power consumption. By making use of the advantages, the display device is used as a display portion of a portable information processing device such as a notebook computer or a display portion of a portable small game player.
In the personal computer or the small game player, a display system is often mounted with an image processing device besides the display device. Here, the display system indicates a system having a function of conducting processing of receiving a result of operation processing performed in a central processing unit (hereinafter referred to as CPU) and displaying an image in a display portion. Further, the image processing device indicates a device which receives the result of operation performed in the CPU and forms image data to be sent to the display device in the display system. Further, the display device indicates a device that displays the image data formed in the image processing device as an image in the display portion. The display portion indicates a region which is comprised of a plurality of pixels and in which an image is displayed.
In order to perform a high-speed display of a large amount of image data, the image processing device is often constituted by an operation processing device dedicated for image processing (hereinafter referred to as GPU: graphic processing unit), a video random access memory (hereinafter referred to as the VRAM) which is a storage device for storing image data, a display processing device, and the like.
Here, the GPU indicates a dedicated circuit that is specialized in a function of conducting operation processing for forming image data, or a circuit partly including a circuit having a function of conducting operation processing for forming image data. Therefore, in the case where part or all of the operation processing for forming image data is performed in the CPU, the CPU includes the GPU. Further, the image data indicates information on color and gradation of a display image, and indicates an electric signal of a type that can be stored in the storage device. The VRAM is stored with image data for one screen. Further, the display processing device is comprised by a circuit having a function of forming an image signal that is sent to the display device from the image data. The image signal indicates an electric signal for varying gradation of the display portion in the display device. For example, in the case of a liquid crystal display device, the image signal corresponds to a voltage signal applied to a pixel electrode.
FIG. 2A is a block structural diagram of a first conventional example, and FIG. 2B is a block structural diagram of a second conventional example. In FIG. 2A, a display system 200 is constituted by an image processing device 202, a display device 203 and a display controller 204, and exchanges data and a control signal with a CPU 201. The image processing device 202 is constituted by a GPU 205, a VRAM 206, and a display processing circuit 207. On the other hand, in FIG. 2B, a display system 210 is constituted by an image processing device 212, a display device 213, and a display controller 214, and exchanges data and a control signal with a CPU 211. The image processing device 212 is constituted by a GPU 215, a GPU 216, a VRAM 217, a VRAM 218, and a display processing circuit 219. Dual port RAMs, in which write can be conducted with one port while read can be conducted with another port, are often used as the VRAMs 206, 217 and 218.
Hereinafter, the operation of the display system will be described as to a case of displaying an image in which structural components constituting the image (hereinafter referred to as image structural component) are a character 301 and a background 302 and in which the character 301 moves about, as shown in FIG. 3.
First, the first conventional example shown in FIG. 2A is described. The CPU 201 performs data operations on the position and direction of the character 301, the position of the background 302, and the like. The operation results are transmitted to the display system 200 to be received by the GPU 205. The GPU 205 conducts operation processing for converting the operation results of the CPU 201 into image data. For example, the GPU 205 conducts operation processing on the formation of the image data of the character 301, the formation of the image data of the background 302, overlapping of the image data, and the like to thereby convert color and gradation of a display image into data expressed by binary numbers. The image data is stored into the VRAM 206, and is periodically read out in accordance with display timing. The read image data is converted into an image signal in the display processing circuit 207, and then is transmitted to the display device 203. Here, in the case of, for example, a liquid crystal display device, the display processing circuit 207 corresponds to a circuit for conducting conversion to a voltage signal, such as a DAC (DA converter), and the image signal corresponds to analog data in accordance with the gradation of the pixel of the display portion. A display timing control of the display device 203 is conducted by the display controller 204.
Next, the second conventional example shown in FIG. 2B is explained. The CPU 211 performs data operations on the position and direction of the character 301, the position of the background 302, and the like. The operation results are sent to the display system 210, and the GPU 215 and the GPU 216 respectively receive the results necessary for performing operations. In this conventional example, the GPU 215 receives the operation results on the position and direction of the character 301 among the operation results in the CPU. Further, the GPU 216 receives the operation results on the position of the background 302 and the like among the operation results in the CPU. Subsequently, the GPU 215 forms image data of the character 301. The formed image data of the character is stored into the VRAM 217. Further, the GPU 216 forms image data of the background 302. The formed image data of the background is stored into the VRAM 218. Then, the GPU 215 and the GPU 216 synchronize each other and read out the character image data stored in the VRAM 217 and the background image data stored in the VRAM 218, and composition of the image data is conducted in the GPU 216. The composed whole image data is converted into an image signal in accordance with display timing in the display processing circuit 219, and then transmitted to the display device 213. A display timing control of the display device 213 is conducted by the display controller 214.
In the first conventional example shown in FIG. 2A, the image data of the character and the background is formed in the GPU 205, and thus, the operation amount is enormous in the case where the image data of the character and the background is frequently updated. On the other hand, the VRAM 206 is required to have a storage capacitance enough to store image data corresponding to one screen. Further, the image data corresponding to one screen needs to be read from the VRAM 206 every time re-imaging (hereinafter referred to as image refresh) of a display image for each frame is conducted in the display device. Therefore, read is conducted even in the case where the displayed image is not updated at all, and thus, the power consumption in the VRAM 206 is large. Accordingly, when a high-definition and multi-gradation image display is performed, the operation amount of the GPU 205 further increases, and the storage capacitance of the VRAM 206 further increases, which leads to a further increase of power consumption at the time of image refresh.
On the other hand, in the second conventional example shown in FIG. 2B, the formation of the character image data and the formation of the background image data are separately conducted by the GPU 215 and the GPU 216. Therefore, even if the image data of the character and the background is frequently updated, the operation processing amount in each of the GPUs is smaller than that of the GPU 205 in the first conventional example. However, the fact remains that two VRAMs are required, that is, a large amount of storage capacitance is required. Further, overlapping processing of the character image data and the background image data is conducted every time the image refresh is conducted in the display device. Therefore, the image data also needs to be periodically read from the VRAM 217 and the VRAM 218. That is, read is conducted even in the case where the character image data or the background image data is not updated at all, and thus, the power consumption is large. Accordingly, when a high-definition and multi-gradation image display is performed, the power consumption in the VRAM 217 and in the VRAM 218 increases.
As described above, the structures of the conventional display systems have the following problems in performing a high-definition and multi-gradation image display at a high imaging speed in the display device. That is, there are given a problem (1) in that the GPU is required to have a considerable operation ability, and thus, the chip size of the GPU is increased, and a problem (2) in that the VRAM is required to have a large amount of storage capacitance, and thus, the chip size of the VRAM is increased. These problems lead to an increase of a mounting area or mounting volume of the image processing device. Further, there is given a problem (3) in that a large amount of image data needs to be read from the VRAM at the time of image refresh, which leads to an increase of power consumption.